1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a structure of a monolithic power MOSFET (metal-oxide-semiconductor field effect transistor) having capability of high power; high speed; and high frequency switching operation.
2. Description of the Prior Art
Conventionally, different structures have been known and employed for a high power; high speed, and high frequency device having a low on-resistance.
FIG. 1 is a cross-sectional view showing a structure of a conventional monolithic conductivity alterable MOSFET. First, referring to FIG. 1, the conventional conductivity modulated MOSFET (referred to as a CAT device hereinafter) will be described. Briefly stated, the CAT device is adapted such that an n.sup.+ -type semiconductor substrate to be a drain region in the planar vertical type DSAMOS (diffusion self aligned MOS) structure formed using a conventional double diffusion method is replaced by a p.sup.+ -type drain/collector layer. More particularly, the CAT device comprises a p-type (p.sup.+ -type) semiconductor substrate 7, which is a drain/collector region, having a high impurity concentration, an n-type epitaxial layer 6, which is a drain drift layer, epitaxially grown on one surface of the p.sup.+ -type semiconductor substrate 7, p-type island regions 5 formed, as base regions, in predetermined regions on one surface of the n-type epitaxial layer 6, n.sup.+ -type impurity diffusion regions 4 formed, as source/emitter regions, on one surface of the p-type island regions, gate electrodes 2 formed, through a gate insulating film 3, on the n-type epitaxial layer 6 between the adjacent p-type island regions 5, a source/emitter electrode 1 formed on the p-type island regions 5 and the impurity diffusion layers 4. A drain/collector electrode 8 is formed on the other surface of the p.sup.+ -type substrate 7.
The gate electrode 2 is formed extending to the n.sup.+ -type source/emitter regions 4, so that an inversion layer, i.e., channel is formed in the p-type island region immediately thereunder in response to the voltage applied thereto.
The n.sup.+ region 4 and the p-type island region 5 are formed by ion plantation and diffusion, using as a mask the gate insulating film 3 comprising, for example, SiO.sub.2 and the gate electrode 2. Electrons flow through the path of the source/emitter electrode 1, the n.sup.+ source/emitter region 4, the inversion layer formed in the region immediately under the gate electrode 2 within the p-type island region 5, the drain drift layer 6 and the drain/collector layer 7.
The source/emitter electrode 1 is connected to a source/emitter terminal S/E, the gate electrode 2 is connected to a gate terminal G, and the drain/collector electrode 8 is connected to a drain/collector terminal D/C.
FIG. 2 is an equivalent circuit diagram of the CAT device shown in FIG. 1.
The CAT device shown in FIG. 1 ideally comprises a series connection of an MOSFET having an n.sup.+ -type region 4 as its source, a p-type island region 5 as its channel region, and an n-type epitaxial layer 6 as its drain, and a pin diode D2 having the n-type epitaxial layer 6 as its cathode and a p.sup.+ -type substrate 7 as its anode. However, as shown in an equivalent circuit diagram of FIG. 2, the CAT device inevitably includes a parasitic thyristor comprising an npn transistor TR1 having the n.sup.+ -type impurity diffusion region 4 as its emitter, the p-type region 5 as its base, and the n-type epitaxial layer 6 as its collector, and a pnp transistor TR2 having the p-type region 5 as its emitter, the n-type epitaxial layer 6 as its base, and the p.sup.+ -type substrate 7 as its collector.
Now, the characteristics and the operation of the CAT device shown in FIG. 1 and FIG. 2 will be described.
First, the characteristics will be simply described. When a terminal G and a terminal S/E are short-circuited, and the reverse bias voltage is applied between a terminal D/C and the terminal S/E, a pin diode D2 is reversely biased, resulting in a reverse bias blocking characteristic of the CAT device. When the terminal G and the terminal S/E are short-circuited, and the forward bias voltage is applied between the terminal D/C and the terminal S/E, a diode D1 comprising the p-type island region 5 and the epitaxial layer 6 is reversely biased, resulting in a forward bias blocking characteristic of the CAT device.
Now, referring to FIGS. 1 and 2, the operation of the CAT device will be described.
When the voltage larger than the threshold voltage of a MOSFET is applied between the gate terminal G and the source/emitter electrode terminal S/E, the inversion layer, i.e., channel is formed in the p region under the gate electrode 2, so that the MOSFET is rendered conductive (on-state), and electrons are injected into the drain drift layer 6. At the same time, there occurs a pin diode operating phenomenon in the pin diode D2, so that holes are injected from the p.sup.+ drain/collector region 7 into the drain drift layer 6. This causes a conductivity of the drain drift layer 6 to increase, so that the CAT device is turned on with low on-resistance. In such a case, the terminal S/E is connected to a ground or negative potential, and the terminal D/C is connected to a positive potential.
In order to turn off the CAT device, the terminals G and S/E will be short-circuited (i.e. made to be the same potential), and the voltage applied between the terminals is made smaller than the threshold voltage of the CAT device. This causes the MOSFET to become an off-state, so that supply of electrons to the drain drift layer 6 is stopped. When the turn off operation of the CAT device is initiated, a large quantity of minority carriers (holes) injected until then (during an on-state of the device) is concentrated on the drain drift layer 6. The holes are injected into the P.sup.+ region 7, so that the current by the corresponding quantity of holes flows into the p-type region 5. If such a phenomenon continues, the degree of concentration of holes on the drain drift layer 6 reduces, whereas the CAT device gradually converts to an off-state. In order to completely turn off the CAT device, plasma of remaining holes and electrons should be completely annihilated by recombination and the like.
The foregoing is a description of the operation of the CAT device where there occurs, at the time of turn off of the CAT device, no latch-up phenomenon in the parasitic thyrister comprising the parasitic transistor TR1 and the parasitic transistor TR2. However, the biggest problem with the CAT device is that the parasitic thyrister causes a latch-up phenomenon at a low current level. If and when the parasitic thyrister causes a latch-up phenomenon and becomes an on-state, the CAT device has no control capability of the gate, and becomes difficult to be turned off. The latch-up phenomenon of the parasitic thyrister is caused by the fact that the parasitic npn transistor TR1 and the parasitic pnp transistor TR2 in the thyrister portion provide mutually a positive feed back operation with a high current density at the time of turn on of the CAT device. The conditions that the parasitic thyrister becomes an on-state through the latch-up phenomenon at the time of turn off are that the sum of respective direct current amplification factors h.sub.FE of the npn transistor TR1 and the pnp transistor TR2 is larger than 1, and the voltage drop by the hole current across resistance R.sub.s in the p-type base region 5 of the transistor TR1 is larger than the saturation voltage between the emitter and base thereof, e.g., more than 0.4 to 0.8 V at 300.degree. K.
FIG. 3 is a cross sectional view showing another conventional CAT device which reduced, to some extent, the above described latch-up phenomenon of the parasitic thyrister. A modified CAT device shown in FIG. 3 comprises a p.sup.+ -type of central base region 50 having a high impurity concentration and formed in the central portion of a p-type base region 5, and a n.sup.+ -type buffer layer 9 formed between a drain drift layer 6 and a p.sup.+ -type drain/collector layer 7. The other construction is the same as that of the CAT device shown in FIG. 1. An equivalent circuit of the modified CAT device shown in FIG. 3 is identical to the circuit shown in FIG. 2.
The modified CAT device is adapted such that the direct current amplification factor h.sub.FE of a parasitic npn transistor TR1 is reduced by the p.sup.+ -type of central base region 50 having a high impurity concentration and the direct current amplification factor h.sub.FE of a parasitic pnp transistor TR2 is reduced by controlling injection of holes from the p.sup.+ -type drain/collector layer 7 to the drain drift layer 6 by the n.sup.+ -type buffer layer 9. Therefore, a current level required for a latch-up phenomenon by the parasitic thyrister at the time of turn on of the CAT device is increased, so that the parasitic thyrister cannot be easily turned on.
However, this modified CAT device has disadvantages that the latch-up phenomenon of the parasitic thyrister can not be fully eliminated even if such modified CAT device is used and that the time of turn off of the CAT device becomes longer since holes accumulated in the drain drift layer 6 are blocked by the p.sup.+ -type drain/collector layer 7 at the time of turn off of the CAT device.
As described above, the conventional CAT device used as a high power; high speed; and high frequency switching element has the disadvantage of a narrow operational control range by the gate (gate-control range), since the CAT device should be operated in the region smaller than the current level required for a latch-up phenomenon by the parasitic thyrister so as to be normally operated, because of the low current level thereof.